1 tm file number 4884.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 pentium?is a registered trademark of intel corporation. | amd?is a registered trademark of advanced micro devices, inc. athlon is a trademark of advanced micro devices, inc. | ultrafet?is a registered trademark of intersil corporation. hip6601a, hip6603a synchronous-recti?d buck mosfet drivers the hip6601a and hip6603a are high frequency, dual mosfet drivers speci?ally designed to drive two power n-channel mosfets in a synchronous-recti?d buck converter topology. these drivers combined with a hip630x multi-phase buck pwm controller and intersil ultrafets form a complete core-voltage regulator solution for advanced microprocessors. the hip6601a drives the lower gate in a synchronous- recti?r to 12v, while the upper gate can be independently driven over a range from 5v to 12v. the hip6603a drives both upper and lower gates over a range of 5v to 12v. this drive-voltage ?xibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. the output drivers in the hip6601a and hip6603a have the capacity to ef?iently switch power mosfets at frequencies up to 2mhz. each driver is capable of driving a 3000pf load with a 30ns propagation delay and 50ns transition time. both products implement bootstrapping on the upper gate with only an external capacitor required. this reduces implementation complexity and allows the use of higher performance, cost effective, n-channel mosfets. adaptive shoot-through protection is integrated to prevent both mosfets from conducting simultaneously. features drives two n-channel mosfets adaptive shoot-through protection internal bootstrap device supports high switching frequency - fast output rise time - propagation delay 30ns small 8 lead soic and epsoic package dual gate-drive voltages for optimal ef?iency three-state input for output stage shutdown supply under voltage protection applications core voltage supplies for intel pentium?iii, amd athlon microprocessors high frequency low pro?e dc-dc converters high current low voltage dc-dc converters related literature technical brief tb363 ?uidelines for handling and processing moisture sensitive surface mount devices (smds) pinout hip6601acb, hip6603acb (soic) HIP6601ABE, hip6603abe (epsoic) top view block diagram ordering information part number temp. range ( o c) package pkg. no. hip6601acb 0 to 85 8 ld soic m8.15 hip6603acb 0 to 85 8 ld soic m8.15 hip6601acb-t 8 ld soic tape and reel hip6603acb-t 8 ld soic tape and reel HIP6601ABE 0 to 85 8 ld epsoic m8.15b hip6603abe 0 to 85 8 ld epsoic m8.15b HIP6601ABE-t 8 ld epsoic tape and reel hip6603abe-t 8 ld epsoic tape and reel ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase pvcc vcc lgate pvcc vcc pwm +5v 10k 10k control logic shoot- through protection boot ugate phase lgate gnd ? vcc for hip6601a ? pvcc for hip6603a data sheet september 2000
2 typical application - 3 channel converter using hip6301 and hip6601a gate drivers +5v boot ugate phase lgate pwm vcc +12v +5v boot ugate phase lgate pwm vcc pvcc drive +12v +5v boot ugate phase lgate pwm vcc +12v +v core pgood vid fs gnd isen3 isen2 isen1 pwm3 pwm2 pwm1 vsen main vfb vcc +5v comp hip6601a control hip6301 pvcc drive hip6601a pvcc drive hip6601a hip6601a, hip6603a
3 absolute maximum ratings thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v supply voltage (pvcc) . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.3v boot voltage (v boot - v phase ). . . . . . . . . . . . . . . . . . . . . . . .15v input voltage (v pwm ) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 7v ugate . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to v pvcc + 0.3v esd rating human body model (per mil-std-883 method 3015.7) . . . . .3kv machine model (per eiaj ed-4701 method c-111). . . . . . . .200v operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . 0 o c to 85 o c maximum operating junction temperature . . . . . . . . . . . . . . 125 o c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v 10% supply voltage range, pvcc . . . . . . . . . . . . . . . . . . . . . 5v to 12v thermal resistance (note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 epsoic package. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 f or details. electrical speci?ations recommended operating conditions, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc hip6601a, f pwm = 1mhz, v pvcc = 12v - 4.4 6.2 ma hip6603a, f pwm = 1mhz, v pvcc = 12v - 2.5 3.6 ma upper gate bias current i pvcc hip6601a, f pwm = 1mhz, v pvcc = 12v - 200 430 a hip6603a, f pwm = 1mhz, v pvcc = 12v - 1.8 3.3 ma power-on reset vcc rising threshold 9.7 9.95 10.4 v vcc falling threshold 9.0 9.2 9.5 v pwm input input current i pwm v pwm = 0 or 5v (see block diagram) - 500 - a pwm rising threshold 3.45 3.6 - v pwm falling threshold - 1.45 1.55 v ugate rise time t rugate v pvcc = 12v, 3nf load - 20 - ns lgate rise time t rlgate v pvcc = 12v, 3nf load - 50 - ns ugate fall time t fugate v pvcc = 12v, 3nf load - 20 - ns lgate fall time t flgate v pvcc = 12v, 3nf load - 20 - ns ugate turn-off propagation delay t pdlugate v pvcc = 12v, 3nf load - 30 - ns lgate turn-off propagation delay t pdllgate v pvcc = 12v, 3nf load - 20 - ns shutdown window 1.4 - 3.6 v shutdown holdoff time - 230 - ns output upper drive source impedance r ugate v pvcc = 5v - 1.7 3.0 ? v pvcc = 12v - 3.0 5.0 ? upper drive sink impedance r ugate v pvcc = 5v - 2.3 4.0 ? v pvcc = 12v - 1.1 2.0 ? lower drive source current i lgate v pvcc = 5v, hip6603a 400 580 - ma v pvcc = 12v, hip6603a 500 730 - ma v pvcc = 5v or 12v, hip6601a 500 730 - ma lower drive sink impedance r lgate v pvcc = 5v or 12v - 1.6 4.0 ? hip6601a, hip6603a
4 functional pin description ugate (pin 1) upper gate drive output. connect to gate of high-side power n-channel mosfet. boot (pin 2) floating bootstrap supply pin for the upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor provides the charge to turn on the upper mosfet. see the internal bootstrap device section under description for guidance in choosing the appropriate capacitor value. pwm (pin 3) the pwm signal is the control input for the driver. the pwm signal can enter three distinct states during operation, see the three-state pwm input section under description for further details. connect this pin to the pwm output of the controller. gnd (pin 4) bias and reference ground. all signals are referenced to this node. lgate (pin 5) lower gate drive output. connect to gate of the low-side power n-channel mosfet. vcc (pin 6) connect this pin to a +12v bias supply. place a high quality bypass capacitor from this pin to gnd. pvcc (pin 7) for the hip6601a, this pin supplies the upper gate drive bias. connect this pin from +12v down to +5v. for the hip6603a, this pin supplies both the upper and lower gate drive bias. connect this pin to either +12v or +5v. phase (pin 8) connect this pin to the source of the upper mosfet and the drain of the lower mosfet. the phase voltage is monitored for adaptive shoot-through protection. this pin also provides a return path for the upper gate drive. description operation designed for versatility and speed, the hip6601a and hip6603a dual mosfet drivers control both high-side and low-side n-channel fets from one externally provided pwm signal. the upper and lower gates are held low until the driver is initialized. once the vcc voltage surpasses the vcc rising threshold (see electrical speci?ations), the pwm signal takes control of gate transitions. a rising edge on pwm initiates the turn-off of the lower mosfet (see timing diagram). after a short propagation delay [t pdllgate ], the lower gate begins to fall. typical fall times [t flgate ] are provided in the electrical speci?ations section. adaptive shoot-through circuitry monitors the lgate voltage and determines the upper gate delay time [t pdhugate ] based on how quickly the lgate voltage drops below 2.2v. this prevents both the lower and upper mosfets from conducting simultaneously or shoot-through. once this delay period is complete the upper gate drive begins to rise [t rugate ] and the upper mosfet turns on. timing diagram pwm ugate lgate t pdllgate t flgate t pdhugate t rugate t pdlugate t fugate t pdhlgate t rlgate hip6601a, hip6603a
5 a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lower mosfet. a short propagation delay [t pdlugate ] is encountered before the upper gate begins to fall [t fugate ]. again, the adaptive shoot- through circuitry determines the lower gate delay time, t pdhlgate . the phase voltage is monitored and the lower gate is allowed to rise after phase drops below 0.5v. the lower gate then rises [t rlgate ], turning on the lower mosfet. three-state pwm input a unique feature of the hip660x drivers is the addition of a shutdown window to the pwm input. if the pwm signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed when the pwm signal moves outside the shutdown window. otherwise, the pwm rising and falling thresholds outlined in the electrical specifications determine when the lower and upper gates are enabled. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a 2.2v threshold, at which time the ugate is released to rise. adaptive shoot-through circuitry monitors the phase voltage during ugate turn-off. once phase has dropped below a threshold of 0.5v, the lgate is allowed to rise. phase continues to be monitored during the lower gate rise time. if phase has not dropped below 0.5v within 250ns, lgate is taken high to keep the bootstrap capacitor charged. if the phase voltage exceeds the 0.5v threshold during this period and remains high for longer than 2 s, the lgate transitions low. both upper and lower gates are then held low until the next rising edge of the pwm signal. power-on reset (por) function during initial startup, the vcc voltage rise is monitored and gate drives are held low until a typical vcc rising threshold of 9.95v is reached. once the rising vcc threshold is exceeded, the pwm input signal takes control of the gate drives. if vcc drops below a typical vcc falling threshold of 9.2v during operation, then both gate drives are again held low. this condition persists until the vcc voltage exceeds the vcc rising threshold. internal bootstrap device both drivers feature an internal bootstrap device. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor must have a maximum voltage rating above vcc + 5v. the bootstrap capacitor can be chosen from the following equation: where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is de?ed as the allowable droop in the rail of the upper drive. as an example, suppose a huf76139 is chosen as the upper mosfet. the gate charge, q gate , from the data sheet is 65nc for a 10v upper gate drive. we will assume a 200mv droop in drive voltage over the pwm cycle. we ?d that a bootstrap capacitance of at least 0.325 f is required. the next larger standard value capacitance is 0.33 f. gate drive voltage versatility the hip6601a and hip6603a provide the user total ?xibility in choosing the gate drive voltage. the hip6601a lower gate drive is ?ed to vcc [+12v], but the upper drive rail can range from 12v down to 5v depending on what voltage is applied to pvcc. the hip6603a ties the upper and lower drive rails together. simply applying a voltage from 5v up to 12v on pvcc will set both driver rail voltages. power dissipation package power dissipation is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating junction temperature of 125 o c. the maximum allowable ic power dissipation for the so8 package is approximately 800mw. when designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the driver is approximated as: where f sw is the switching frequency of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l is the upper and lower gate charge determined by mosfet selection and any external capacitance added to the gate pins. the i ddq v cc product is the quiescent power of the driver and is typically 30mw. the power dissipation approximation is a result of power transferred to and from the upper and lower gates. but, the internal bootstrap device also dissipates power on-chip during the refresh cycle. expressing this power in terms of the upper mosfet total gate charge is explained below. c boot q gate ? v boot ----------------------- - p 1.05f sw 3 2 -- - v u q u v l q l + ?? ?? i ddq v cc + = hip6601a, hip6603a
6 the bootstrap device conducts when the lower mosfet or it s body diode conducts and pulls the phase node toward gnd. while the bootstrap device conducts, a current path is formed that refreshes the bootstrap capacitor. since the upper gate is driving a mosfet, the charge removed from the bootstrap capacitor is equivalent to the total gate charge of the mosfet. therefore, the refresh power required by the bootstrap capacitor is equivalent to the power used to charge the gate capacitance of the mosfet. where q loss is the total charge removed from the bootstrap capacitor and provided to the upper gate load. the 1.05 factor is a correction factor derived from the following characterization. the base circuit for characterizing the drivers for different loading pro?es and frequencies is provided. c u and c l are the upper and lower gate load capacitors. decoupling capacitors [0.15 f] are added to the pvcc and vcc pins. the bootstrap capacitor value is 0.01 f. in figure 1, c u and c l values are the same and frequency is varied from 50khz to 2mhz. pvcc and vcc are tied together to a +12v supply. curves do exceed the 800mw cutoff, but continuous operation above this point is not recommended. figure 2 shows the dissipation in the driver with 3nf loading on both gates and each individually. note the higher upper gate power dissipation which is due to the bootstrap device refresh cycle. again pvcc and vcc are tied together and to a +12v supply. test circuit the impact of loading on power dissipation is shown in figure 3. frequency is held constant while the gate capacitors are varied from 1nf to 5nf. vcc and pvcc are tied together and to a +12v supply. figures 4 through 6 show the same characterization for the hip6603a with a +5v supply on pvcc and vcc tied to a +12v supply. since both upper and lower gate capacitance can vary, figure 7 shows dissipation curves versus lower gate capacitance with upper gate capacitance held constant at three different values. these curves apply only to the hip6601a due to power supply con?uration. p refresh 1 2 -- - f sw q loss v pvcc 1 2 -- - f sw q u v u == boot ugate phase lgate pwm pvcc gnd vcc 0.15 f 0.15 f 100k ? 2n7002 2n7002 0.01 f c l c u +5v or +12v +12v hip660x +5v or +12v 1000 800 600 400 200 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 3nf pvcc = vcc = 12v c u = c l = 1nf c u = c l = 2nf c u = c l = 4nf c u = c l = 5nf figure 1. power dissipation vs frequency 1000 800 600 400 200 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 3nf pvcc = vcc = 12v c u = 3nf c l = 3nf figure 2. 3nf loading profile c l = 0nf c u = 0nf hip6601a, hip6603a
7 typical performance curves figure 3. power dissipation vs loading figure 4. power dissipation vs frequency (hip6603a) figure 5. 3nf loading profile (hip6603a) figure 6. variable loading profile (hip6603a) figure 7. power dissipation vs frequency (hip6601a) 600 500 400 300 200 1.0 2.0 3.0 4.0 5.0 power (mw) gate capacitance (c u = c l ) (nf) frequency = 800khz pvcc = vcc = 12v 100 frequency = 500khz frequency = 200khz 400 320 240 160 80 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 5nf c u = c l = 4nf c u = c l = 3nf pvcc = 5v vcc = 12v c u = c l = 1nf c u = c l = 2nf 300 240 180 120 60 0 500 1000 1500 2000 power (mw) frequency (khz) c u = c l = 3nf pvcc = 5v, vcc = 12v c u = 3nf c l = 3nf c l = 0nf c u = 0nf 250 200 150 100 50 1.0 2.0 3.0 4.0 5.0 power (mw) gate capacitance (c u = c l ) (nf) frequency = 800khz pvcc = 5v, 0 frequency = 500khz frequency = 200khz vcc = 12v 1.0 2.0 3.0 4.0 5.0 400 power (mw) frequency (khz) c u = 5nf pvcc = 5v, vcc = 12v 350 300 200 150 100 c u = 3nf c u = 1nf hip6601a, hip6603a
8 hip6601a, hip6603a small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15b 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.056 0.066 1.43 1.68 - a1 0.001 0.005 0.03 0.13 - b 0.0138 0.0192 0.35 0.49 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.31 3.39 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.64 6 n8 87 0 o 8 o 0 o 8 o - p - 0.090 - 2.286 11 p1 - 0.090 - 2.286 11 rev. 0 6/00 notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ? and ?1 are thermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.
9 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 hip6601a, hip6603a small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?o series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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